The increasing complexity of systems and semiconductor process is resulting in more defects in the System On Chip (SoC) design process. The yield of these SoCs is directly linked to the memories on the SoC as around 60-70% of the silicon area on the chip is covered by the memories. Different types of memories are used for various operations on chips, like storage, temporary calculations, synchronization, buffering etc. Due to such a large presence of memories on chip, the chip yield is directly linked to the memory yield and hence to the memory defect level. In the newer technologies the degree of defects in the memories have increased to a great extent due to shrinking dimensions. In this context neither controlled process nor design can help in improving the SoC's yield as shrinking gate lengths have resulted in newer processes where the defect levels have gone beyond the control of the process and design. The only method, which can still help in enhancing the yield of the SoC, is to repair the faulty cases by providing redundant parts.
Many different types of redundant elements have been introduced in the previous inventions to deal with this problem. There are several proposed schemes for repairing faulty memories as well. These include providing redundancy for row, column, word, bit, soft memory or another piece of memory, which can be classified into two types:                1. The type-1 redundancy includes all the techniques which implement the redundancy inside the memory itself. Spare row, spare bit slice, or spare column redundancy can be put into this category.        2. The type-2 redundancy includes of techniques which provide redundancy as an external element to the memory. Spare memory, spare soft memory etc. can be put in this category.        
The problem with using the type-1 redundancy in memory system is that it results in modified timing characteristics (setup/hold/access/cycle). This type of redundancy also results in increased development cycle time for the memory compilers. For instance, it is observed that the column redundancy leads to increased repair time for the memory after power on. In the row redundancy, the setup and hold time of the memory are increased which puts a limit on the number of redundant rows allowed. The problem with the type-2 redundancy is seen in terms of the memory performance as the soft routed memories can be routed all round the SoC which results in unnecessary routing congestion. Also soft memories cannot be used for multi port memories as considerably more effort is required in designing multiport soft memories. The timing characteristics (setup/hold/access) of the memory are modified by the soft memories as well. The area is another concern as soft memories are made using standard cells in a standard cell library which take more area than ASIC memories. This puts a restriction on the number of redundant elements allowed on an ASIC. Even in a case where a hard memory of same type is used instead of the soft memory, there is a significant area overhead as besides the storage elements other logic blocks in a memory like address decoders, I/O sections etc. are also duplicated.
At system level, memory redundancy results in another problem when there are several small memories on a chip. These small memories are either used to form a bigger memory or are used individually but in vicinity of each other on a chip. In such situations, the present techniques provide a redundant memory for each individual memory. But not all the memories fail on a wafer and it is observed that most of the time the redundant memories are wasted. Therefore putting redundancy for each memory is highly inefficient as it increases the overhead in terms of the memory area and fuse area and results in timing overhead as well. The redundant memories also impact the setup and hold times of the memories.
Hence there is need for a memory system with redundant memories that reduces the area overhead in terms of silicon and fuse area. There is also need for memory system with redundant memories that do not affect the timing characteristics of the memory. Collectively there is also need to provide a shared redundancy from the total bit size point of view for all memories present on a chip. The present invention provides a memory system incorporating shared redundant elements for the memories on any SoC or Application Specific Integrated Circuit (ASIC). The present invention also provides a shared redundant memory architecture. In this context when there are several small memories on a SoC, two different embodiments of a modified redundant memory are provided for use as a shared redundant element for different memory systems. The number and type of shared redundant memories on a SoC depends on the interconnect architecture and number of the small memories.